Atomic-Level EUV Precision
High-NA EUV prints every layer at a 13.5 nm wavelength with sub-nanometer overlay — each transistor lands exactly where physics intends.
2NM PROCESS NODE · HIGH-NA EUV
Silicon at the Atomic Frontier
NANOVA's N2 platform pairs gate-all-around transistors with high-NA EUV lithography — more performance, less power, at wafer scale.
- Process node
- 2 nm
- Peak performance
- +15%
- Power per transistor
- −30%
- Yield target
- 99.9%
Capabilities
Engineered for Precision
Precision is not a feature of N2 — it is the product.
30% Less Power Per Transistor
Gate-all-around nanosheet architecture cuts leakage at the source: phones last longer and data centers draw measurably less.
ISO Class 1 Yield Discipline
Every wafer runs through 400+ steps under ISO Class 1 control, with in-line metrology verifying each layer and a 99.9% die yield target.
Process
From RTL to Shipping Silicon
Three gates stand between your design and volume delivery.
-
01
Design & Simulation
Your RTL enters our calibrated N2 flow. Timing, parasitics and thermal behavior close before a single wafer is exposed.
-
02
Fabrication
Wafers advance through 400+ steps on high-NA EUV scanners, each layer verified by in-line metrology in ISO Class 1 cleanrooms.
-
03
Validation & Delivery
Die pass electrical, thermal and reliability qualification, then ship with full yield analytics attached.
Field Reports
Trusted by Silicon Teams
We taped out a 24-core SoC on N2 and silicon came back within 0.3% of simulated timing. First-pass success at 2nm is unheard of.
Power per transistor dropped a third. Our flight compute modules now run fanless — a straight line from fab to product.
Yields held above target across three full-volume runs. NANOVA's defect analytics surface every anomaly before it ships.
Pricing
Capacity Plans
Transparent wafer pricing, from first tape-out to full-volume production.
Research
$5,000/ month
For universities and early-stage silicon programs.
- Shared MPW shuttle slots
- N2 PDK and reference flows
- Design-rule support desk
- 4-week queue priority
Production
$24,000/ month
For product teams shipping at volume.
- Dedicated wafer starts
- Full high-NA EUV options
- In-line metrology dashboard
- Named yield engineer
- 99.9% yield SLA
Enterprise
Custom
For hyperscale and foundry partners.
- Reserved fab capacity blocks
- Custom process tuning
- On-site NANOVA liaison engineer
- 24/7 priority support
FAQ
Questions, Answered
When does N2 enter volume production?
N2 is in risk production now; the full volume ramp opens in Q3 2026. Monthly MPW shuttles already run for research customers.
What are the minimum order volumes?
MPW shuttles accept designs from a single die. Dedicated wafer starts begin at 12 wafers per quarter; reserved capacity starts at 500 wafers per month.
Which certifications does NANOVA hold?
Our fabs are certified to ISO 9001, IATF 16949 and ISO 14001, with ISO Class 1 cleanroom audit reports available under NDA.
How is customer IP protected?
Design data is encrypted at rest with customer-held keys, mirrored into an air-gapped fab network, and purged from shuttle clusters after delivery.
What are typical lead times?
Standard flows run 12 weeks of fabrication plus 2 weeks of validation; fast-turn MPW shuttles compress the same path to 8 weeks.
Get Started
Put 2nm Silicon on Your Roadmap
Reserve N2 wafer capacity or request the process design kit — a silicon engineer replies within one business day.
Talk to Sales